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| never stop thinking. hys64d32301[g/h]u?5?b hys[64/72]d64xxx[g/h]u?[5/6]?b hys[64/72]d128xxx[g/h]u?[5/6]?b 184-pin unbuffered doublel-data-rate memory modules udimm ddr sdram data sheet, rev. 1.2, may 2005 memory products
edition 2005-05 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. template: mp_a4_s_rev312 / 3 / 2005-03-18 hys64d32301[g/h]u?5?b, hys[64/72 ]d64xxx[g/h]u?[5/6]?b, hys[64/72]d128xxx[g/h]u?[5/6]?b revision history: 2005-05, rev. 1.2 previous version: rev. 1.1 page subjects (major cha nges since last revision) 6 added new product type 16 added raw card c diagram 25 updated i dd values 27 aded spd code for new product type we listen to your comments any information within this do cument that you feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send us your proposal (including a reference to this document) to: techdoc.mp@infineon.com data sheet 4 rev. 1.2, 2005-05 hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 current conditions and specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table of contents data sheet 5 rev. 1.2, 2005-05 08132003-ivb4-kl4j 184-pin unbuffered doublel-data-rate memory modules udimm hys64d32301[g/h]u?5?b hys[64/72]d64xxx[g/h]u?[5/6]?b hys[64/72]d128xxx[g/h]u?[5/6]?b 1overview 1.1 features ?184-pin unbuffered doublel-data-rate memory modules (ecc and non-parity) for pc and workstation main memory applications ? one rank 32m 6 4m x 64, 64m 72 and two ranks 128m 64, 128m 72 organization ? tandard double data rate synchronous drams () single +2.5v ( 0.2v) power supply ? built with 512-mbit in p-tsopii-66 package ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? all inputs and outputs sstl_2 compatible ? serial presence detect with e2prom ? jedec standard mo-206 form factor: 133.35 mm 31.75 mm 4.00 mm max. ? standard reference layout ? gold plated contacts ? ddr400 speed grade supported ? lead-free 1.2 description the hys64d32301[g/h]u?5?b, hys[64/72]d64xxx[g/h]u? [5/6]?b, hys[64/72]d128xxx[g/h]u?[5/6]?b, and are industry standard 184-pin unbuffered doublel- data-rate memory modules (udimm) organized as 32m 64m (256 mb), 64m 64 (512 mb), 128m 64 (1 gb) for non-parity and 64m 72 (512 mb), 128m 72 (1 gb) for ecc main memory applications. the memory array is designed with 512mbit double data rate synchronous drams. a variety of decoupling capacitors are mounted on the printed circuit board . the dimms feature serial presence detect (spd) based on a serial e2prom device using the 2-pin i2c protocol. the first 128 bytes are programmed with configuration data and the seco nd 128 bytes are available to the customer. table 1 performance part number speed code ?5 ?6 unit speed grade component ddr400b ddr333b ? module pc3200?3033 pc2700?2533 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules overview data sheet 6 rev. 1.2, 2005-05 08132003-ivb4-kl4j note: all part numbers end wit h a place code designating the silicon-die revision. reference in formation available on request. example: hys72d64300hu-6-b, indicating rev. b dies are used for sdram components. the compliance code is printed on the module labels desc ribing the speed sort (for example ?pc2700?), the latencies and spd code definition (for exampl e ?20330? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jede c spd code definiton version 0), and the raw card used for this module. table 2 ordering information type compliance code desc ription sdram technology pc3200 (cl=3.0) hys64d64300gu?5?b pc3200u?30330?a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300gu?5?b pc3200u?30330?a0 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320gu?5?b pc3200u?30330?b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320gu?5?b pc3200u?30330?b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) pc2700 (cl=2.5) hys64d64300gu?6?b pc2700u?25330?a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300gu?6?b pc2700u?25330?a0 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320gu?6?b pc2700u?25330?b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320gu?6?b pc2700u?25330?b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) pc3200 (cl=3.0) hys64d32301hu?5?b pc3200u?30330?c0 one rank 256 mb dimm 512 mbit ( 16) hys64d64300hu?5?b pc3200u?30330?a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu?5?b pc3200u?30330?a0 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320hu?5?b pc3200u?30330?b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu?5?b pc3200u?30330?b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) pc2700 (cl=2.5) hys64d64300hu?6?b pc2700u?25330?a0 one rank 512 mb dimm 512 mbit ( 8) hys72d64300hu?6?b pc2700u?25330?a0 one rank 512 mb ecc-dimm 512 mbit ( 8) hys64d128320hu?6?b pc2700u?25330?b0 two ranks 1 gb dimm 512 mbit ( 8) hys72d128320hu?6?b pc2700u?25330?b0 two ranks 1 gb ecc-dimm 512 mbit ( 8) 1) rcd: row-column-delay data sheet 7 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration 2 pin configuration the pin configuration of the unbuffered ddr sdram dimm is listed by function in table 3 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 4 and table 5 respectively. the pin numbering is depicted in figure 1 . table 3 pin configuration of udimm pin# name pin type buffer type function clock signals 137 ck0 i sstl clock signals 2:0 note: for clock net loading see block diagram, ck0 is nc on 1r 16 nc nc ? 16 ck1 i sstl 76 ck2 i sstl 138 ck0 i sstl complement clock signals 2:0 note: for clock net loading see block diagram, ck0 is nc on 1r 16 nc nc ? 17 ck1 i sstl 75 ck2 i sstl 21 cke0 i sstl clock enable rank 0 111 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 157 s0 i sstl chip select rank 0 158 s1 i sstl chip select rank 1 note: 2-rank module nc nc ? note: 1-rank module 154 ras i sstl row address strobe 65 cas i sstl column address strobe 63 we i sstl write enable address signals 59 ba0 i sstl bank address bus 2:0 52 ba1 i sstl 48 a0 i sstl address bus 11:0 43 a1 i sstl 41 a2 i sstl 130 a3 i sstl 37 a4 i sstl 32 a5 i sstl 125 a6 i sstl 29 a7 i sstl hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration data sheet 8 rev. 1.2, 2005-05 08132003-ivb4-kl4j 122 a8 i sstl address bus 11:0 27 a9 i sstl 141 a10 i sstl ap i sstl 118 a11 i sstl 115 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 167 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 2 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 6 dq2 i/o sstl 8 dq3 i/o sstl 94 dq4 i/o sstl 95 dq5 i/o sstl 98 dq6 i/o sstl 99 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 19 dq10 i/o sstl 20 dq11 i/o sstl 105 dq12 i/o sstl 106 dq13 i/o sstl 109 dq14 i/o sstl 110 dq15 i/o sstl 23 dq16 i/o sstl 24 dq17 i/o sstl 28 dq18 i/o sstl 31 dq19 i/o sstl 114 dq20 i/o sstl 117 dq21 i/o sstl table 3 pin configuration of udimm (cont?d) pin# name pin type buffer type function data sheet 9 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration 121 dq22 i/o sstl data bus 63:0 123 dq23 i/o sstl 33 dq24 i/o sstl 35 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 126 dq28 i/o sstl 127 dq29 i/o sstl 131 dq30 i/o sstl 133 dq31 i/o sstl 53 dq32 i/o sstl 55 dq33 i/o sstl 57 dq34 i/o sstl 60 dq35 i/o sstl 146 dq36 i/o sstl 147 dq37 i/o sstl 150 dq38 i/o sstl 151 dq39 i/o sstl 61 dq40 i/o sstl 64 dq41 i/o sstl 68 dq42 i/o sstl 69 dq43 i/o sstl 153 dq44 i/o sstl 155 dq45 i/o sstl 161 dq46 i/o sstl 162 dq47 i/o sstl 72 dq48 i/o sstl 73 dq49 i/o sstl 79 dq50 i/o sstl 80 dq51 i/o sstl 165 dq52 i/o sstl 166 dq53 i/o sstl 170 dq54 i/o sstl 171 dq55 i/o sstl 83 dq56 i/o sstl 84 dq57 i/o sstl 87 dq58 i/o sstl 88 dq59 i/o sstl 174 dq60 i/o sstl 175 dq61 i/o sstl table 3 pin configuration of udimm (cont?d) pin# name pin type buffer type function hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration data sheet 10 rev. 1.2, 2005-05 08132003-ivb4-kl4j 178 dq62 i/o sstl data bus 63:0 179 dq63 i/o sstl 44 cb0 i/o sstl check bit 0 note: ecc type module nc nc ? note: non-ecc module 45 cb1 i/o sstl check bit 1 note: ecc type module nc nc ? note: non-ecc module 49 cb2 i/o sstl check bit 2 note: ecc type module nc nc ? note: non-ecc module 51 cb3 i/o sstl check bit 3 note: ecc type module nc nc ? note: non-ecc module 134 cb4 i/o sstl check bit 4 note: ecc type module nc nc ? note: non-ecc module 135 cb5 i/o sstl check bit 5 note: ecc type module nc nc ? note: non-ecc module 142 cb6 i/o sstl check bit 6 note: ecc type module nc nc ? note: non-ecc module 144 cb7 i/o sstl check bit 7 note: ecc type module nc nc ? note: non-ecc module 5 dqs0 i/o sstl data strobe bus 7:0 note: see block diagram for corresponding dq signals 14 dqs1 i/o sstl 25 dqs2 i/o sstl 36 dqs3 i/o sstl 56 dqs4 i/o sstl 67 dqs5 i/o sstl 78 dqs6 i/o sstl 86 dqs7 i/o sstl 47 dqs8 i/o sstl data strobe 8 note: ecc type module nc nc ? note: non-ecc module table 3 pin configuration of udimm (cont?d) pin# name pin type buffer type function data sheet 11 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration 97 dm0 i sstl data mask bus 7:0 107 dm1 i sstl 119 dm2 i sstl 129 dm3 i sstl 149 dm4 i sstl 159 dm5 i sstl 169 dm6 i sstl 177 dm7 i sstl 140 dm8 i sstl data mask 8 note: ecc type module nc nc ? note: non-ecc module eeprom 92 scl i cmos serial bus clock 91 sda i/o od serial bus data 181 sa0 i cmos slave address select bus 2:0 182 sa1 i cmos 183 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage 184 v ddspd pwr ? eeprom power supply 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 v ddq pwr ? i/o driver power supply table 3 pin configuration of udimm (cont?d) pin# name pin type buffer type function hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration data sheet 12 rev. 1.2, 2005-05 08132003-ivb4-kl4j 7, 38, 46, 70, 85, 108, 120, 148, 168 v dd pwrzp ? power supply 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 v ss gnd ? ground plane other pins 82 v ddid ood v dd identification note: pin in tristate, indicating v dd and v ddq nets connected on pcb 9, 10, 71, 90, 101, 102, 103, 113, 163, 173 nc nc ? not connected pins not connected on infineon udimms table 3 pin configuration of udimm (cont?d) pin# name pin type buffer type function data sheet 13 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration table 4 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 5 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules pin configuration data sheet 14 rev. 1.2, 2005-05 08132003-ivb4-kl4j figure 1 pin configuration 184-pin, udimm - 0 0 $ 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 6 3 3 $ 1 $ - $ 1 . # . # $ 1 $ - $ 1 # + % . # $ 1 $ 1 . # $ 1 $ 1 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 ! ! $ 1 ! # " . # # + . # $ - . # # " . # # " . # 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n . # ! . # $ 1 $ - $ 1 $ 1 ! $ 1 $ - $ 1 $ 1 # " . # # + . # 6 3 3 ! ! 0 6 $ $ 1 6 2 % & 6 3 3 $ 1 3 6 $ $ . # 6 3 3 $ 1 6 $ $ 1 # + $ 1 $ 1 $ 1 $ 1 $ 1 . # $ 1 $ 1 3 # + 6 3 3 $ 1 $ 1 $ 1 ! $ 1 3 $ 1 # " . # ! " ! # + % $ 1 $ 1 3 ! ! $ 1 $ 1 $ 1 ! $ 1 ! ! # " . # $ 1 3 . # # " . # # " . # 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n " ! # + 3 ) $ % & 2 / . 4 3 ) $ % 6 3 3 $ 1 $ - $ 1 $ 1 $ 1 3 $ - $ 1 . # $ 1 ! . # $ - $ 1 . # $ 1 $ - $ 1 3 ! 3 ! $ 1 $ 1 2 ! 3 3 . # $ 1 $ 1 $ 1 $ 1 $ 1 3 ! 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n 0 i n $ 1 3 $ 1 $ 1 $ 1 $ 1 # + $ 1 3 $ 1 $ 1 $ 1 3 $ 1 . # 3 # , $ 1 $ 1 $ 1 " ! $ 1 7 % # ! 3 $ 1 3 $ 1 . # $ 1 # + 6 $ $ 1 $ 1 6 3 3 $ 1 6 $ $ $ 1 6 3 3 3 $ ! 6 $ $ 1 6 3 3 6 $ $ 1 6 3 3 6 $ $ 6 3 3 6 $ $ 6 3 3 6 $ $ 1 6 3 3 6 $ $ 1 6 3 3 6 $ $ 6 3 3 6 $ $ ) $ 6 $ $ 1 6 3 3 6 $ $ 1 6 $ $ 6 $ $ 1 6 3 3 6 $ $ 6 3 3 6 $ $ 1 6 3 3 6 $ $ 1 6 $ $ 6 3 3 6 $ $ 1 6 3 3 6 $ $ 1 6 $ $ 6 $ $ 1 6 3 3 6 $ $ 1 6 $ $ 3 0 $ data sheet 15 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules block diagram 3blockdiagram figure 2 block diagram udimm raw card a 64, 1 rank, 8 notes 1. v dd = v ddq , therefore v ddid strap open 2. dq, dqs, dm resistors are 22 ? 5% 3. ban, an, ras , cas , we resistors are 5.1 ? 5% table 6 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 256 mb 32m 64 1 32m 16 4 13/2/9 8k 64 ms 7.8 ms 512 mb 64m 64 1 64m 88 13/2/11 8k 64ms7.8ms 512 mb 64m 72 1 64m 88 13/2/11 8k 64ms7.8ms 1gb 128m 64 2 64m 8 16 13/2/12 8k 64 ms 7.8 ms 1gb 128m 72 2 64m 8 18 13/2/12 8k 64 ms 7.8 ms - 0 " $ 3 $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / " ! " ! 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ " ! " ! ! ! n 2 ! 3 # ! 3 7 % # + % 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 3 t r a p s e e . o t e 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ ) $ 3 # , 3 ! $ 3 ! 3 ! 3 ! 6 3 3 3 # , 3 ! $ ! ! ! 7 0 % table 7 clock signal loads clock input number of sdrams note ck0, ck0 2 sdrams ? hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules block diagram data sheet 16 rev. 1.2, 2005-05 08132003-ivb4-kl4j figure 3 block diagram udimm raw card c 64 1 rank 16 notes 1. v dd = v ddq , therefore v ddid strap open 2. dq, dqs, dm resistors are 22 ? 5% 3. ban, an, ras , cas , we resistors are 7.5 ? 5% ck1, ck1 3 sdrams ? ck2, ck2 3 sdrams ? table 7 clock signal loads clock input number of sdrams note mpbd1051 s0 dm1 dqs1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm0 dqs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 d0 dm3 dqs3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm2 dqs2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 d1 dm5 dqs5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm4 dqs4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 d2 d3 dm7 dqs7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dm6 dqs6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 ba0 - ba1 a0 - an ras cas we cke0 ba0 - ba1: sdrams d0 - d3 a0 - an: sdrams d0 - d3 ras: sdrams d0 - d3 cas: sdrams d0 - d3 we: sdrams d0 - d3 cke: sdrams d0 - d3 ldm cs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ldm cs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ldm cs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 ldm cs ldqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 udm udqs i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 v dd : spd eeprom e0 v dd / v ddq : sdrams d0 - d3 v ref : sdrams d0 - d3 v ss : sdrams d0 - d3 strap: see note 1 v ddspd v dd / v ddq v ref v ss v ddid scl sad sa0 sa1 sa2 v ss scl sad a0 a1 a2 wp e0 table 8 clock signal loads clock input number of sdrams note ck0, ck0 nc ? ck1, ck1 2 sdrams ? ck2, ck2 2 sdrams ? data sheet 17 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules block diagram figure 4 block diagram udimm raw card b (x64, 2 ranks, x8) note: 4. v dd = v ddq , therefore v ddid strap open 5. dq, dqs, dm resistors are 22 ? 5% 6. ban, an, ras , cas , we resistors are 3 ? 5% - 0 " $ 3 " ! " ! 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ " ! " ! ! ! n 2 ! 3 # ! 3 7 % # + % # + % $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 3 $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ $ $ $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ $ $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 3 t r a p s e e . o t e 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ ) $ 3 # , 3 ! $ 3 ! 3 ! 3 ! 6 3 3 3 # , 3 ! $ ! ! ! 7 0 % table 9 clock signal loads clock input number of sdrams note ck0, ck0 4 sdrams ? ck1, ck1 6 sdrams ? ck2, ck2 6 sdrams ? hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules block diagram data sheet 18 rev. 1.2, 2005-05 08132003-ivb4-kl4j figure 5 block diagram udimm raw card a 72, 1rank, 8, ecc note: note: v dd = v ddq , therefore v ddid strap open 7. dq, dqs, dm resistors are 22 ? 5% 8. ban, an, ras , cas , we resistors are 5.1 ? 5% - 0 " $ 3 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ $ $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ - $ 1 3 # " # " # " # " # " # " # " # " $ - $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / " ! " ! 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ " ! " ! ! ! n 2 ! 3 # ! 3 7 % # + % $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - # 3 $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ 3 t r a p s e e . o t e 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ ) $ 3 # , 3 ! $ 3 ! 3 ! 3 ! 6 3 3 3 # , 3 ! $ ! ! ! 7 0 % table 10 clock signal loads clock input number of sdrams note ck0, ck0 3 sdrams ? ck1, ck1 3 sdrams ? ck2, ck2 3 sdrams ? data sheet 19 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules block diagram figure 6 block diagram udimm raw card b 72, 2ranks, 8, ecc notes 1. v dd = v ddq , therefore v ddid strap open 2. dq, dqs, dm resistors are 22 ? 5% 3. ban, an, ras , cas , we resistors are 3 ? 5% - 0 " $ $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ $ $ $ $ $ $ - $ 1 3 $ 1 3 # " # " # " # " # " # " # " # " $ 3 # , 3 ! $ 3 ! 3 ! 3 ! 6 3 3 % 3 # , 3 ! $ ! ! ! 7 0 6 $ $ 3 0 $ % % 0 2 / - % 6 $ $ 6 $ $ 1 3 $ 2 ! - s $ $ 6 2 % & 3 $ 2 ! - s $ $ 6 3 3 3 $ 2 ! - s $ $ $ - 3 $ 2 ! - s $ $ 6 $ $ 3 0 $ 6 $ $ 6 $ $ 1 6 2 % & 6 3 3 6 $ $ ) $ 3 t r a p s e e . o t e 3 3 $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ $ $ $ - $ 1 3 $ 1 3 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ 1 $ $ # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / # 3 $ - $ 1 3 ) / ) / ) / ) / ) / ) / ) / ) / " ! " ! 3 $ 2 ! - s $ $ ! ! n 3 $ 2 ! - s $ $ 2 ! 3 3 $ 2 ! - s $ $ # ! 3 3 $ 2 ! - s $ $ 7 % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ # + % 3 $ 2 ! - s $ $ " ! " ! ! ! n 2 ! 3 # ! 3 7 % # + % # + % table 11 clock signal loads clock input number of sdrams note ck0, ck0 6 sdrams ? ck1, ck1 6 sdrams ? ck2, ck2 6 sdrams ? hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules block diagram data sheet 20 rev. 1.2, 2005-05 08132003-ivb4-kl4j figure 7 clock net wiring $ 2 ! - , o a d s 2 ? $ ) - - # o n n e c t o r $ 2 ! - $ 2 ! - $ 2 ! - $ 2 ! - $ 2 ! - $ 2 ! - $ 2 ! - , o a d s 2 ? $ ) - - # o n n e c t o r $ 2 ! - $ 2 ! - # a p # a p $ 2 ! - $ 2 ! - $ 2 ! - , o a d s 2 ? $ ) - - # o n n e c t o r $ 2 ! - # a p $ 2 ! - # a p $ 2 ! - # a p $ 2 ! - , o a d s 2 ? $ ) - - # o n n e c t o r $ 2 ! - # a p # a p # a p $ 2 ! - # a p $ 2 ! - , o a d s 2 ? $ ) - - # o n n e c t o r # a p # a p $ 2 ! - # a p # a p # a p # + # + # a p $ $ 2 3 $ 2 ! - i n p u t c a p a c i t a n c e p & ? data sheet 21 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules electrical characteristics 4 electrical characteristics 4.1 operating conditions attention: permanent damage to the device may occur if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operation should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 12 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v ? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) pd ? 1 ? w ? short circuit output current i out ?50? ma? table 13 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 8) input low (logic0) voltage v il(dc) ? 0.3 v ref ? 0.15 v 8) input voltage level, ck and ck inputs v in(dc) ? 0.3 v ddq + 0.3 v 8) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 8)6) hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules electrical characteristics data sheet 22 rev. 1.2, 2005-05 08132003-ivb4-kl4j vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 7) input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 8)9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 8) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v 8) output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 8) 1) 0 c t a 70 c 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% vref (dc). vref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal terminatio n resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) v id is the magnitude of the difference between th e input level on ck and the input level on ck . 7) the ration of the pull-up current to the pull-down current is specified for the same temperat ure and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) inputs are not recognized as valid until v ref stabilizes. 9) values are shown per component table 14 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) clock cycle time t ck 5 8 ? ? ns cl = 3.0 2)3)4)5) 6 12 7.5 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) table 13 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. data sheet 23 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules electrical characteristics control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)6) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) data-out high-impedance time from ck/ck t hz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) write command to 1 st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.45 ns tsopii 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.55 ns tsopii 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs t hp ? t qhs ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)8) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)9) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)10) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)10) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)10) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)10) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) auto-refresh to ac tive/auto-refresh command period t rfc 70 ? 72 ? ns 2)3)4)5) table 14 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules electrical characteristics data sheet 24 rev. 1.2, 2005-05 08132003-ivb4-kl4j active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rasmin ns 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) auto precharge write recovery + precharge time t dal t ck 2)3)4)5)11) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) average periodic refresh interval t refi ?7.8 ?7.8 s 2)3)4)5)12) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) these parameters guarantee device timing, but they are not necessarily tested on each device. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input sl ew rate specifications of th e device. when no writes were previously in progress on the bus, dqs will be transitioning from hi-z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning fr om high to low at this time, depending on t dqss . 9) the maximum limit for this parameter is not a device limit. t he device operates with a greater value for this parameter, but system performance (bus turnar ound) degrades accordingly. 10) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ns, measured between v ih(ac) and v il(ac) . 11) for each of the terms, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. 12) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. table 14 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. data sheet 25 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules electrical characteristics 4.2 current conditions and specification table 15 i dd specification for hys[64/72]d[32/64/128]3xxhu?5?b product type hys64d32301hu?5?b hys64d64300hu?5?b hys64d64300gu?5?b hys72d64300hu?5?b hys72d64300gu?5?b hys64d128320hu?5?b hys64d128320gu?5?b hys72d128320hu?5?b unit note 1)2) 1) dram component currents only 2) test condition fo r maximum values: v dd =2.7v, t a =10c organization 256mb 512mb 512mb 1gb 1gb 64 64 64 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 ?5 symbol typ. max. typ. max. typ. max. typ. max. typ. max. i dd0 400 480 640 800 720 900 950 1180 1070 1330 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 460 560 720 880 810 990 1030 1260 1160 1420 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 10 20 10 30 20 40 30 64 31 70 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 120 140 240 290 270 320 480 580 540 650 ma 5) i dd2q 80 100 150 210 170 230 300 420 340 470 ma 5) i dd3p 50 60 100 130 110 140 190 260 220 290 ma 5) i dd3n 170 200 310 380 350 420 620 750 700 850 ma 5) i dd4r 480 580 680 800 770 900 990 1180 1120 1320 ma 3)4) i dd4w 500 600 720 840 810 950 1030 1220 1160 1370 ma 3) i dd5 820 980 1640 1960 1850 2210 1950 2340 2200 2630 ma 3) i dd6 11 20.8 22 42 30 50 45 80 50 90 ma 3) i dd7 1140 1360 2080 2480 2340 2790 2390 2860 2690 3210 ma 3)4) hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules electrical characteristics data sheet 26 rev. 1.2, 2005-05 08132003-ivb4-kl4j table 16 i dd specification for hys[64/72]d[64/128]3xxhu?6?b product type hys64d64300hu?6?b hys64d64300gu?6?b hys72d64300hu?6?b hys72d64300gu?6?b hys64d128320hu?6?b hys64d128320gu?6?b hys72d128320hu?6?b unit note 1)2) 1) dram component currents only 2) test condition fo r maximum values: v dd =2.7v, t a =10c organization 512 mb 512 mb 1 gb 1 gb 64 72 64 72 1rank 1rank 2ranks 2ranks ?6 ?6 ?6 ?6 symbol typ. max. typ. max. typ. max. typ. max. i dd0 600 720 680 810 880 1050 990 1180 ma 3) 3) the module i ddx values are calculated from the component i ddx data sheet values as: m i ddx [component] + n i dd3n [component] with m and n number of components of rank 1 and 2; n =0 for 1 rank modules i dd1 680 800 770 900 960 1130 1080 1270 ma 3)4) 4) dq i/o ( i ddq ) currents are not included into calculations: module i dd values will be measured differently depending on load conditions i dd2p 10 30 10 40 30 64 290 70 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 200 240 230 270 400 480 450 540 ma 5) i dd2q 140 190 150 220 270 380 310 430 ma 5) i dd3p 90 120 100 140 180 240 200 270 ma 5) i dd3n 280 330 320 370 560 660 630 740 ma 5) i dd4r 620 720 690 810 900 1050 1010 1180 ma 3)4) i dd4w 650 760 730 860 930 1090 1040 1220 ma 3) i dd5 1480 1760 1670 1980 1760 2090 1980 2350 ma 3) i dd6 22 42 24 47 43 80 49 94 ma 3) i dd7 1870 2230 2110 2510 2150 2560 2420 2880 ma 3)4) data sheet 27 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents 5spdcontents chapter contains all spd codes for the products as listed in table 2 ? table 17 ?spd codes for hys64d32301hu?5?b? on page 27 ? table 18 ?spd codes for hys[64/72] d[64/128][300/320]gu?5?b? on page 30 ? table 19 ?spd codes for hys[64/72]d[64/128][300/320]hu?5?b? on page 33 ? table 20 ?spd codes for hys[64/72] d[64/128][300/320]gu?6?b? on page 36 ? table 21 ?spd codes for hys[64/72]d[64/128][300/320]hu?6?b? on page 39 table 17 spd codes for hys64d32301hu?5?b product type hys64d32301hu?5?b organization 256 mb 64 1 rank ( 16) label code pc3200u?30331 jedec spd revision rev. 1.0 byte# description hex 0 programmed spd bytes in e2prom 80 1 total number of bytes in e2prom 08 2 memory type (ddr = 07h) 07 3 number of row addresses 0d 4 number of column addresses 0a 5 number of dimm ranks 01 6 data width (lsb) 40 7 data width (msb) 00 8 interface voltage levels 04 9 t ck @ cl max (byte 18) [ns] 50 10 t ac sdram @ cl max (byte 18) [ns] 50 11 error correction support 00 12 refresh rate 82 13 primary sdram width 10 14 error checking sdram width 00 15 t ccd [cycles] 01 16 burst length supported 0e 17 number of banks on sdram device 04 18 cas latency 1c 19 cs latency 01 20 write latency 02 21 dimm attributes 20 22 component attributes c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 24 t ac sdram @ cl max -0.5 [ns] 50 25 t ck @ cl max -1 (byte 18) [ns] 75 26 t ac sdram @ cl max -1 [ns] 50 hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 28 rev. 1.2, 2005-05 08132003-ivb4-kl4j 27 t rpmin [ns] 3c 28 t rrdmin [ns] 28 29 t rcdmin [ns] 3c 30 t rasmin [ns] 28 31 module density per rank 40 32 t as, tcs [ns] 60 33 t ah, tch [ns] 60 34 t ds [ns] 40 35 t dh [ns] 40 36 - 40 not used 00 41 t rcmin [ns] 37 42 t rfcmin [ns] 41 43 t ckmax [ns] 28 44 t dqsqmax [ns] 28 45 t qhsmax [ns] 50 46 not used 00 47 dimm pcb height 01 48 - 61 not used 00 62 spd revision 10 63 checksum of byte 0-62 16 64 jedec id code of infineon (1) c1 65 jedec id code of infineon (2) 00 66 jedec id code of infineon (3) 00 67 jedec id code of infineon (4) 00 68 jedec id code of infineon (5) 00 69 jedec id code of infineon (6) 00 70 jedec id code of infineon (7) 00 71 jedec id code of infineon (8) 00 72 module manufacturer location xx 73 part number, char 1 36 74 part number, char 2 34 75 part number, char 3 44 76 part number, char 4 33 77 part number, char 5 32 78 part number, char 6 33 table 17 spd codes for hys64d32301hu?5?b product type hys64d32301hu?5?b organization 256 mb 64 1 rank ( 16) label code pc3200u?30331 jedec spd revision rev. 1.0 byte# description hex data sheet 29 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents 79 part number, char 7 30 80 part number, char 8 31 81 part number, char 9 48 82 part number, char 10 55 83 part number, char 11 35 84 part number, char 12 42 85 part number, char 13 20 86 part number, char 14 20 87 part number, char 15 20 88 part number, char 16 20 89 part number, char 17 20 90 part number, char 18 20 91 module revision code 0x 92 test program revision code xx 93 module manufacturing date year xx 94 module manufacturing date week xx 95 module serial number (1) xx 96 module serial number (2) xx 97 module serial number (3) xx 98 module serial number (4) xx 99 - 127 not used 00 table 17 spd codes for hys64d32301hu?5?b product type hys64d32301hu?5?b organization 256 mb 64 1 rank ( 16) label code pc3200u?30331 jedec spd revision rev. 1.0 byte# description hex hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 30 rev. 1.2, 2005-05 08132003-ivb4-kl4j table 18 spd codes for hys[64/72]d[64/128][300/320]gu?5?b product type hys64d64300gu?5?b hys72d64300gu?5?b hys64d128320gu?5?b hys72d128320gu?5?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u?30330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0b 0b 5 number of dimm ranks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 1c 1c 1c 1c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 50 50 27 t rpmin [ns] 3c 3c 3c 3c data sheet 31 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents 28 t rrdmin [ns] 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 31 module density per rank 80 80 80 80 32 t as, tcs [ns] 60 60 60 60 33 t ah, tch [ns] 60 60 60 60 34 t ds [ns] 40 40 40 40 35 t dh [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 43 t ckmax [ns] 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 dimm pcb height 00 00 00 00 48 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 3e 50 3f 51 64 jedec id code of infineon (1) c1 c1 c1 c1 65 - 71 jedec id code of infineon (2 -8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 table 18 spd codes for hys[64/72]d[64/128][300/320]gu?5?b (cont?d) product type hys64d64300gu?5?b hys72d64300gu?5?b hys64d128320gu?5?b hys72d128320gu?5?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u?30330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 32 rev. 1.2, 2005-05 08132003-ivb4-kl4j 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 47 47 30 30 82 part number, char 10 55 55 47 47 83 part number, char 11 35 35 55 55 84 part number, char 12 42 42 35 35 85 part number, char 13 20 20 42 42 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 0x 0x 0x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 table 18 spd codes for hys[64/72]d[64/128][300/320]gu?5?b (cont?d) product type hys64d64300gu?5?b hys72d64300gu?5?b hys64d128320gu?5?b hys72d128320gu?5?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u?30330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex data sheet 33 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents table 19 spd codes for hys[64/72]d[64/128][300/320]hu?5?b product type hys64d64300hu?5?b hys72d64300hu?5?b hys64d128320hu?5?b hys72d128320hu?5?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u?30330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0b 0b 5 number of dimm ranks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 50 11 error correction support 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 1c 1c 1c 1c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 50 50 27 t rpmin [ns] 3c 3c 3c 3c hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 34 rev. 1.2, 2005-05 08132003-ivb4-kl4j 28 t rrdmin [ns] 28 28 28 28 29 t rcdmin [ns] 3c 3c 3c 3c 30 t rasmin [ns] 28 28 28 28 31 module density per rank 80 80 80 80 32 t as, tcs [ns] 60 60 60 60 33 t ah, tch [ns] 60 60 60 60 34 t ds [ns] 40 40 40 40 35 t dh [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 37 37 37 37 42 t rfcmin [ns] 41 41 41 41 43 t ckmax [ns] 28 28 28 28 44 t dqsqmax [ns] 28 28 28 28 45 t qhsmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 dimm pcb height 00 00 00 00 48 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 3e 50 3f 51 64 jedec id code of infineon (1) c1 c1 c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 table 19 spd codes for hys[64/72]d[64/128][300/320]hu?5?b (cont?d) product type hys64d64300hu?5?b hys72d64300hu?5?b hys64d128320hu?5?b hys72d128320hu?5?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u?30330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex data sheet 35 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 48 48 30 30 82 part number, char 10 55 55 48 48 83 part number, char 11 35 35 55 55 84 part number, char 12 42 42 35 35 85 part number, char 13 20 20 42 42 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 0x 0x 0x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 table 19 spd codes for hys[64/72]d[64/128][300/320]hu?5?b (cont?d) product type hys64d64300hu?5?b hys72d64300hu?5?b hys64d128320hu?5?b hys72d128320hu?5?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3200u?30330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 36 rev. 1.2, 2005-05 08132003-ivb4-kl4j table 20 spd codes for hys[64/72]d[64/128][300/320]gu?6?b product type hys64d64300gu?6?b hys72d64300gu?6?b hys64d128320gu?6?b hys72d128320gu?6?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u?25330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0b 0b 5 number of dimm ranks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 11 error correction support 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 0c 0c 0c 0c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 27 t rpmin [ns] 48 48 48 48 data sheet 37 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents 28 t rrdmin [ns] 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 31 module density per rank 80 80 80 80 32 t as, t cs [ns] 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 34 t ds [ns] 45 45 45 45 35 t dh [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 43 t ckmax [ns] 30 30 30 30 44 t dqsqmax [ns] 2d 2d 2d 2d 45 t qhsmax [ns] 55 55 55 55 46 not used 00 00 00 00 47 dimm pcb height 00 00 00 00 48 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 42 54 43 55 64 jedec id code of infineon (1) c1 c1 c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 table 20 spd codes for hys[64/72]d[64/128][300/320]gu?6?b (cont?d) product type hys64d64300gu?6?b hys72d64300gu?6?b hys64d128320gu?6?b hys72d128320gu?6?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u?25330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 38 rev. 1.2, 2005-05 08132003-ivb4-kl4j 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 47 47 30 30 82 part number, char 10 55 55 47 47 83 part number, char 11 36 36 55 55 84 part number, char 12 42 42 36 36 85 part number, char 13 20 20 42 42 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 0x 0x 0x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 table 20 spd codes for hys[64/72]d[64/128][300/320]gu?6?b (cont?d) product type hys64d64300gu?6?b hys72d64300gu?6?b hys64d128320gu?6?b hys72d128320gu?6?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u?25330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex data sheet 39 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents table 21 spd codes for hys[64/72]d[64/128][300/320]hu?6?b product type hys64d64300hu?6?b hys72d64300hu?6?b hys64d128320hu?6?b hys72d128320hu?6?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u?25330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex 0 programmed spd bytes in e2prom 80 80 80 80 1 total number of bytes in e2prom 08 08 08 08 2 memory type (ddr = 07h) 07 07 07 07 3 number of row addresses 0d 0d 0d 0d 4 number of column addresses 0b 0b 0b 0b 5 number of dimm ranks 01 01 02 02 6 data width (lsb) 40 48 40 48 7 data width (msb) 00 00 00 00 8 interface voltage levels 04 04 04 04 9 t ck @ cl max (byte 18) [ns] 60 60 60 60 10 t ac sdram @ cl max (byte 18) [ns] 70 70 70 70 11 error correction support 00 02 00 02 12 refresh rate 82 82 82 82 13 primary sdram width 08 08 08 08 14 error checking sdram width 00 08 00 08 15 t ccd [cycles] 01 01 01 01 16 burst length supported 0e 0e 0e 0e 17 number of banks on sdram device 04 04 04 04 18 cas latency 0c 0c 0c 0c 19 cs latency 01 01 01 01 20 write latency 02 02 02 02 21 dimm attributes 20 20 20 20 22 component attributes c1 c1 c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 75 75 75 75 24 t ac sdram @ cl max -0.5 [ns] 70 70 70 70 25 t ck @ cl max -1 (byte 18) [ns] 00 00 00 00 26 t ac sdram @ cl max -1 [ns] 00 00 00 00 27 t rpmin [ns] 48 48 48 48 hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents data sheet 40 rev. 1.2, 2005-05 08132003-ivb4-kl4j 28 t rrdmin [ns] 30 30 30 30 29 t rcdmin [ns] 48 48 48 48 30 t rasmin [ns] 2a 2a 2a 2a 31 module density per rank 80 80 80 80 32 t as, t cs [ns] 75 75 75 75 33 t ah, t ch [ns] 75 75 75 75 34 t ds [ns] 45 45 45 45 35 t dh [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 t rcmin [ns] 3c 3c 3c 3c 42 t rfcmin [ns] 48 48 48 48 43 t ckmax [ns] 30 30 30 30 44 t dqsqmax [ns] 2d 2d 2d 2d 45 t qhsmax [ns] 55 55 55 55 46 not used 00 00 00 00 47 dimm pcb height 00 00 00 00 48 - 61 not used 00 00 00 00 62 spd revision 00 00 00 00 63 checksum of byte 0-62 42 54 43 55 64 jedec id code of infineon (1) c1 c1 c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 00 00 72 module manufacturer location xx xx xx xx 73 part number, char 1 36 37 36 37 74 part number, char 2 34 32 34 32 75 part number, char 3 44 44 44 44 76 part number, char 4 36 36 31 31 77 part number, char 5 34 34 32 32 78 part number, char 6 33 33 38 38 table 21 spd codes for hys[64/72]d[64/128][300/320]hu?6?b product type hys64d64300hu?6?b hys72d64300hu?6?b hys64d128320hu?6?b hys72d128320hu?6?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u?25330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex data sheet 41 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules spd contents 79 part number, char 7 30 30 33 33 80 part number, char 8 30 30 32 32 81 part number, char 9 48 48 30 30 82 part number, char 10 55 55 48 48 83 part number, char 11 36 36 55 55 84 part number, char 12 42 42 36 36 85 part number, char 13 20 20 42 42 86 part number, char 14 20 20 20 20 87 part number, char 15 20 20 20 20 88 part number, char 16 20 20 20 20 89 part number, char 17 20 20 20 20 90 part number, char 18 20 20 20 20 91 module revision code 0x 0x 0x 0x 92 test program revision code xx xx xx xx 93 module manufacturing date year xx xx xx xx 94 module manufacturing date week xx xx xx xx 95 - 98 module serial number (1 - 4) xx xx xx xx 99 - 127 not used 00 00 00 00 table 21 spd codes for hys[64/72]d[64/128][300/320]hu?6?b product type hys64d64300hu?6?b hys72d64300hu?6?b hys64d128320hu?6?b hys72d128320hu?6?b organization 512 mb 512 mb 1 gbyte 1 gbyte 64 72 64 72 1 rank ( 8) 1 rank ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc2700u?25330 jedec spd revision rev 0.0 r ev 0.0 rev 0.0 rev 0.0 byte# description hex hex hex hex hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules package outlines data sheet 42 rev. 1.2, 2005-05 08132003-ivb4-kl4j 6 package outlines figure 8 raw card c ddr udimm hys6 4d32301hu?5?b (1 rank module) ! ? ! " # - ! 8 " ! # ? ? ! # " x - ) . ? " ! # ? " ! # $ e t a i l o f c o n t a c t s ? # ? " ? ? " u r r m a x a l l o w e d / n % # # m o d u l e s o n l y data sheet 43 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules package outlines figure 9 raw card a ddr udimm hys64d64 300hu?[5/6/7]?b (1 rank module) 92 1 1.27 1 0.05 0.1 b a c detail of contacts 0 . 2 3 min. 2.5 0.2 3.8 93 0.13 0.1 1.8 a 0.1 c b 17.8 10 184 92 1.27 0.1 c 0.4 b 31.75 0.13 2.7 max. 6.62 0.1 1 2.36 64.77 95 x c b a ?0.1 6.35 120.65 1.27 = 2.175 49.53 92 0.1 4 0.1 a bc 128.95 133.35 b 0.15 a c a burr max. 0.4 allowed l-dim-184-32 hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules package outlines data sheet 44 rev. 1.2, 2005-05 08132003-ivb4-kl4j figure 10 raw card a ddr udimm hys72d 64300hu?[5/6/7f]?b (1 rank module) 1 92 0.13 1 0.05 1.27 0.1 b a c detail of contacts 0.2 3 min. 3.8 93 2.5 0.2 1.8 0.1 c a 0.1 b 17.8 184 10 4 0.1 0.1 ac b 128.95 a 133.35 2.7 max. 0.15 b a c 6.35 0.1 2.36 1 64.77 ?0.1 c a b 1.27 x 95 120.65 = 2.175 6.62 49.53 92 b 0.13 31.75 1.27 c 0.1 0.4 1) burr max. 0.4 allowed 1) on ecc modules only l-dim-184-30 data sheet 45 rev. 1.2, 2005-05 08132003-ivb4-kl4j hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules package outlines figure 11 raw card b ddr udimm hys64d 128320hu?[5/6/7]?b (2 ranks module) 4 c b 0.1 a 0.1 2.36 1 0.1 c 64.77 ?0.1 a b 95 133.35 128.95 1.27 x= 2.175 6.62 120.65 a 6.35 1.27 0.15 4 max. 49.53 92 0.4 31.75 b 0.13 c b 0.1 a c 0.1 detail of contacts 0.2 1.27 3.8 0.13 3 min. 93 0.2 2.5 1 0.05 0.1 ac b 1.8 0.1 b a c 184 10 17.8 burr max. 0.4 allowed l-dim-184-33 hys[64/72]d[32/64/128 ]xxx[g/h]u?[5/6]?b unbuffered ddr sdram modules package outlines data sheet 46 rev. 1.2, 2005-05 08132003-ivb4-kl4j figure 12 raw card b ddr udimm hys72d128320hu?[5/6/7]?b (2 rank module) 1 1 92 92 0.1 1.27 c 4 max. 0.4 a 0.1 b c a 133.35 128.95 a 0.15 b c 0.1 4 b 0.13 31.75 a 64.77 2.36 0.1 ?0.1 6.35 95 x 1.27 = 120.65 6.62 c b 2.175 49.53 0.05 1 1.27 0.2 detail of contacts 0.1 abc 2.5 0.2 17.8 10 184 93 0.13 3.8 3 min. 0.1 1.8 b a 0.1 c 1) burr max. 0.4 allowed 1) on ecc modules only l-dim-184-31 published by infineon technologies ag www.infineon.com |
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